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ISL55141, ISL55142, ISL55143
Data Sheet July 17, 2006 FN6230.0
High-Speed 18V CMOS Comparators
ISL55141, ISL55142, ISL55143 integrated circuits are high-speed, wide input common-mode range comparators. They provide three-state window comparators in a high voltage CMOS process (18V). Each comparator has dual receive thresholds, CVA and CVB, for establishing minimum 1-VIH and maximum 0-VIL voltage levels. These devices can accept inputs from a number of logic families, such as TTL, ECL, CMOS, LVCMOS, LVDS and CML. Two bits of output per comparator provide the test controller with qualification of a comparator input into three states. The two output bits work with a separate user supply to establish VOH, VOL levels compatibility with the system's controller logic levels. Fast propagation delay (9.5ns typical at 50mV overdrive) makes this family compatible with high-speed digital test systems. The 18V range enables the comparator input to operate over a wide input range. Two references per input enable and three state digitization of input with voltage swings of up to 13V common mode. The operating frequency of these devices is typically 65MHz. High voltage CMOS process makes these devices ideal for large voltage swing applications, such as special test voltages levels associated with Flash devices or power supervision applications and may avoid the need for test bus isolation relay(s).
Features
* 18V I/O range * 65MHz operation * 9.5ns typical propagation delay * Programmable input thresholds * User defined comparator output levels * Common-mode range includes negative rails * Small footprints in QFN packages * Power-down current <10A * Pb-free plus anneal available (RoHS compliant)
Applications
* Burn in ATE * Low cost ATE * Fast supervisory power control * Instrumentation
Ordering Information
PART NUMBER PART TEMP. MARKING RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE 16 Ld QFN (Pb-free) PKG. DWG. # L16.4X4A
ISL55141IRZ* 55141IRZ (See Note) ISL55141IVZ* 55141IVZ (See Note) ISL55142IRZ* 55142IRZ (See Note) ISL55142IVZ* 55142IVZ (See Note) ISL55143IRZ* 55143IRZ (See Note)
Functional Block Diagram
DUAL LEVEL COMPARATOR - RECEIVERS VOH QAX VOL VEE VOH QBX VOL VEE x denotes 1, 2 or 4 channels for ISL55141, ISL55142 and ISL55143, respectively CVBX VCC CVAX VINPX VCC
14 Ld TSSOP M14.173 (Pb-free) 20 Ld QFN (Pb-free) L20.5x5
20 Ld TSSOP M20.173 (Pb-free) 36 Ld TQFN (Pb-free) L36.6X6
* Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL55141, ISL55142, ISL55143 Pinouts
ISL55141 SINGLE DEVICE (4X4 QFN) ISL55142 SINGLE DEVICE (5X5 QFN)
TOP VIEW
VEE NC NC PD NC
TOP VIEW
VINP0 CVB0 17 CVB1 16 15 VINP1 14 CVA1 13 VCC 12 VEE 11 NC 6 QA0 7 QB0 8 QA1 9 QB1 10 NC 20 CVB1 19 VINP1 18 CVA1 17 NC 16 VCC 15 VEE 14 NC 13 NC 12 QB1 11 QA1 CVA0 19
16 NC NC QA QB 1 2 3 4 5 VOL
15
14
13 12 NC 11 CVB 10 VINP 9 CVA PD VEE VCC VOH VOL
20 1 2 3 4 5
18
6 VOH
7 VEE
8 VCC
ISL55141 (TSSOP)
ISL55142 (TSSOP)
TOP VIEW
VEE NC NC QA QB VOL VOH 1 2 3 4 5 6 7 14 PD 13 NC 12 CVB 11 VINP 10 CVA 9 VCC 8 VEE CVB0 VINP0 CVA0 PD VEE VCC VOH VOL QA0 ISL55143 QUAD DEVICE (6X6 TQFN) 1 2 3 4 5 6 7 8 9
TOP VIEW
QB0 10
TOP VIEW
VCC VCC VEE VEE NC NC NC NC 29 PD 28 27 CVB0 26 VINP0 25 CVA0 24 CVB1 23 VINP1 22 CVA1 21 CVB2 20 VINP2 19 CVA2 10 VOH 11 VOL 12 VOH 13 VOL 14 VEE 15 VCC 16 CVA3 17 VINP3 18 CVB3
36 NC QA0 QB0 QA1 QB1 QA2 QB2 QA3 QB3 1 2 3 4 5 6 7 8 9
35
34
33
32
31
30
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FN6230.0 July 17, 2006
ISL55141, ISL55142, ISL55143 Pin Descriptions
PIN VEE QAX QBX VOL VOH VCC CVAX VINPX CVBX PD NC Negative supply input Channel A, CVAX reference driven. Comparator output. Channel B, CVBX reference driven. Comparator output. Comparator output logic low supply. Unbuffered analog input that sets all QAX, QBX "low" voltage level. Comparator output logic high supply. Unbuffered analog input that sets all QAX, QBX "high" voltage level. Positive supply input. Channel A comparator reference analog input. Window comparator input. Common to both channel Ax and channel Bx. Channel B comparator reference analog input. Power-down logic input (connect to VEE if not used for power-down). No internal connection. FUNCTION
TABLE 1. CVA-QA AND CVB-QB BASIC COMPARATOR TRUTH TABLE INPUT VINPX CVAX >CVAX CVBX CVBX QAX 0 0 1 1 OUTPUTS* QBX 0 1 0 1
* When QAX/QBX = 1, Output is connect to VOH * When QAX/QBX = 0, Output is connect to VOL
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FN6230.0 July 17, 2006
ISL55141, ISL55142, ISL55143
Absolute Maximum Ratings
VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 19V Input Voltages PD, CVAX, CVBX, VINPX, VOH, VOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VEE -0.5V) to (VCC +0.5V) Output Voltage QAX, QBX . . . . . . . . . . . . . . . . . . . . . (VOL -0.5V) to (VOH +0.5V)
Thermal Information
Thermal Resistance (Typical, Note 1, 2) JA (C/W) 16 Ld QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 75 14 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 90 20 Ld QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 65 20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 80 36 Ld QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 45 Maximum Junction Temperature (Plastic Package) . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. Device temperature is closely tied to data-rates, driver loads and overall pin activity. Review Power Dissipation Considerations for more information.
Recommended Operating Conditions
PARAMETER Device Power Comparator Output High Rail Comparator Output Low Rail Common Mode Input Voltage Range Ambient Temperature Junction Temperature SYMBOL VCC-VEE VOH VOL VCM TA TJ MIN 10 VEE+1 VEE+0.5 VEE -40 27 TYP 15 MAX 18 VCC-0.5 VEE+6 VCC-5 +85 +125 UNITS V V V V C C
pO
Electrical Specifications
PARAMETER DC CHARACTERISTICS Input Offset Voltage Input Bias Current Power-down Current Power-down Time (Note 5) Power-up Time (Note 5) TIMING CHARACTERISTICS Propagation Delay Rise Time (Note 5) Fall Time (Note 5) Propagation Delay Mismatch Maximum Operating Frequency Min Pulse Width COMPARATOR INPUT Input Current Input Capacitance (Note 5)
Test Conditions: VCC = 12V, VEE = -3V, VOH = 5V, VOL = 0V, PD = VEE, CLOAD = 15pF, TA = 25C, unless otherwise specified. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VOS IBIAS IPD tPD tPU
CVAX = CVBX = 1.5V VINPX - CV(A/B)X = 5V PD = VCC
-50 10 8 10 15
50 25 25
mV nA A s s
tpd tr tf tpd FMAXR tWIDR IIN CIN VINPX = VCC or VEE Symmetry 50%
4.0
9.5 1.4 1.5 0.5 65 7.7
15
ns ns ns
2
ns MHz ns
-100
0 2.5
100
nA pF
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FN6230.0 July 17, 2006
ISL55141, ISL55142, ISL55143
Electrical Specifications
PARAMETER DIGITAL OUTPUTS QAX, QBX Output Resistance Output Logic High Voltage Output Logic Low Voltage POWER SUPPLIES, STATIC CONDITIONS Positive Supply DC Current/Comparator Negative Supply Current/Comparator Total Power Dissipation/Comparator ICC IEE P No input data No input data Input data at 40MHz -12.5 +8.25 -8.25 670 12.5 mA mA mW RoutR VOH VOL VOH = 5V, ISOURCE = 1mA VOL = 0V, ISINK = 1mA 18 4.9 0.00 27 4.95 0.05 37 5.0 0.1 V V Test Conditions: VCC = 12V, VEE = -3V, VOH = 5V, VOL = 0V, PD = VEE, CLOAD = 15pF, TA = 25C, unless otherwise specified. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Total Power dissipation per comparator can be approximately calculated from the following: P = (VCC-VEE)*8.25mW + 90pF*(VCC-VEE)^2*f + CL*(VCC-VEE)^2*f where f is the operating frequency and CL is the load capacitance. Because the ISL55142 has two comparators, the power dissipation would be twice of P calculated from the above equation. The ISL55143 would be four times P. NOTES: 3. Lab characterization, room temperature, timing parameters matched stimulus/loads, channel-to-channel skew < 500ps, 1ns maximum by design 4. Note about ICC measurement input can approach 140mA (single comparator) at maximum pattern rates 5. Not 100% Tested
Test Circuits and Waveforms
DATA = 1 DATA = 0 400mV 0V tPDLH 50% tR tPDHL VOH (VH) QAX, QBX 50% VOL (VL) tF
VINPX
FIGURE 1. COMPARATOR PROPAGATION DELAY AND TRANSITION TIME MEASUREMENT POINTS
CVA 2.4V VINP
+ -
VCC
QA
Although there is no electrical difference between the CVA and CVB Inputs, if one defines CVA as being the high threshold and CVB being the low threshold, it becomes easier to understand the utilization of a dual threshold comparator. Essentially this enables the qualification of an incoming signal into three states. In the case pictured, the three states are Valid Low <0.4V, No-man's-land (between 0.4 and 2.4V), Valid High >2.4V. Table 2 shows how the QA/QB truth table would be utilized in the real world.
TABLE 2. QA/QB TRUTH TABLE VINP <0.4V >0.4 and <2.4V >2.4V QA 0 0 1 QB 0 1 1 COMMENT Valid 0 Invalid Valid 1
CVB 0.4V
+ -
VEE
QB
FIGURE 2. THREE-STATE WINDOW COMPARATOR FUNDAMENTALS
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FN6230.0 July 17, 2006
ISL55141, ISL55142, ISL55143 Test Circuits and Waveforms (Continued)
+11 VCC CVA 1.5V CVA = CVB = 1.5V 50mV
+
+5V-VOH
VOL
QA
VINP
1.5V
1.5V -50mV
VINP
tPDLH 50%
tPDHL VOH (5V) 50% VOL (0V)
CVB 1.5V
+ -3 VEE
QB
QX
FIGURE 3. tpd RECEIVER SWITCHING TEST CIRCUIT
FIGURE 4. tpd RECEIVER PROPAGATION DELAY MEASUREMENT POINTS
Application Information
The ISL55141, ISL55142, ISL55143 provide 1, 2 and 4 dual threshold, three-state window comparator(s) in TSSOP or QFN footprints. They offer a combination of speed (10ns Tpd and wide voltage range (18V). This product directly addresses the need for unique common-mode characterisitics while supplying a power-down feature. Figures 3 and 4 show the stimulus setup and measurement points for an example propagation delay measurement. Typical room temperature results are displayed in Figure 11. Figure 4 shows a VINP range of 50mV. In Figure 11 the offset is increased in the horizontal axis from 50mV above and below the reference (1.5V) up to 2.5V above and below the 1.5V reference. Two lines are displayed in Figure 11. One represents the rising-to-rising delay (tPDLH) and the other the falling-to-falling delay (tPDHL).
The truth table for the receivers is given in Table 1. Receiver outputs are not tri-statable, and do not incorporate any on-chip short circuit current protection. Momentary short circuits to GND, or any supply voltage, will not cause permanent damage, but care must be taken to avoid longer duration short circuits. If tolerable to the application, current limiting resistors can be inserted in series with the QAX and QBX outputs to protect the receiver outputs from damage due to overcurrent conditions.
Power-down Features
The ISL55141, ISL55142, ISL55143 PD pin provides a means of reducing current consumption when the device is not in use. Supply currents falls from ~7mA to less than 10A in the power-down mode. The device requires approximately 10s to power-down and 15s to power-up.
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VEE pin is connected to ground, one 0.1F ceramic capacitor should be placed from the VCC pin to ground. A 4.7F tantalum capacitor should then be connected from the VCC pin to ground. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used.
Comparator Features
These three-state window comparators feature high output current capability, and user defined high and low output levels to interface with a wide variety of logic families. Each receiver comprises two comparators and each comparator has an independent threshold level input, making it easy to implement (Minimum1-VIH)/(Maximum 0-VIL) logic level comparator functions. The CVAX and CVBX pins set the threshold levels of the A and B comparators respectively. VOH and VOL set all the comparator output levels, and VOH must be more positive than VOL. These two inputs are unbuffered supply pins, so the sources driving these pins must provide adequate current for the expected load. VOH and VOL typically connect to the power supplies of the logic device driven by the comparator outputs.
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FN6230.0 July 17, 2006
ISL55141, ISL55142, ISL55143
Power Dissipation Considerations
Specifying continuous data rates, driver loads and driver level amplitudes are key in determining power supply requirements as well as dissipation/cooling necessities. Driver output patterns also impact these needs. The faster the pin activity, the greater the need to supply current and remove heat. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
VINP
Power Supply Information
OPTIONAL PROTECTION DIODE VCC
CVA
VOH
QA
where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation in the package
CVB
QB
VOL
Approximate Power Dissipation
(Typ) P = N*[(VCC-VEE)*8.25mW + 90pF*(VCC-VEE)^2*f + CL*(VOH-VOL)^2*f] where: N is the number of comparators in the chip (1 for ISL55141, 2 for ISL55142 and 4 for ISL55143). (f) is the operating frequency. CL is the load capacitor. The power dissipation calculated from the above formula may have an error of 20-25%. The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads. Power also depends on the number of channels changing state and frequency of operation. The extent of continuous active pattern generation/reception will greatly affect dissipation requirements. The user should evaluate various heat sink/cooling options in order to control the ambient temperature part of the equation. This is especially true if the user's applications require continuous, high-speed operation. The reader is cautioned against assuming the same level of thermal performance in actual applications. A careful inspection of conditions in your application should be conducted.
VEE
OPTIONAL PROTECTION DIODE
Circuit design must always take into account the internal EOS/ESD protection structure of the device. Important Note: The QFN package metal plane is used for heat sinking of the device. It is electrically connected to the negative supply potential (VEE). If VEE is tied to ground, the thermal pad can be connected to ground. Otherwise, the thermal pad (VEE) must be isolated from other power planes.
Power Supply Sequencing
The ISL55141, ISL55142, ISL55143 reference every supply with respect to VEE. Therefore, apply VEE, VOL then VCC followed by the CVA and CVB supplies. The comparator VINP pin should not exceed VEE or VCC during power-up. In cases where inputs may exceed voltage rails during power-up, series resistance should be employed to safeguard EOS to the ESD protection diodes.
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FN6230.0 July 17, 2006
ISL55141, ISL55142, ISL55143 Typical Performance Curves
30.0 27.0 24.0 21.0 ICC (mA) ICC (mA) 18.0 15.0 12.0 09.0 06.0 03.0 00.0 10 12 14 VCC - VEE VOLTAGE 16 18 ISL55141 ISL55142 ISL55143
Device installed on Intersil ISL55141, ISL55142, ISL55143 Evaluation Boards.
60 54 48 42 36 30 24 18 12 6 0 3200 1600 800 400 200 100 VCC = 10V 50 25 VINP SQUARE WAVE PERIOD IN ns VCC = 14V VCC = 18V
FIGURE 5. ISL55141, ISL55142, ISL55143 QUIESCENT CURRENT
FIGURE 6. ISL55141 ICC vs FREQUENCY @ 10V, 14V, AND 18V
80 72 64 56 ICC (mA) 48 40 32 24 16 8 0 3200 1600 800 400 200 100 50 25 1 CHANNEL 2 CHANNELS ICC (mA)
200 180 160 140 120 100 80 60 40 20 0 3200 1600 800 400 200 100 1 CHANNEL 50 25 VINP SQUARE WAVE PERIOD IN ns 3 CHANNEL 2 CHANNEL 4 CHANNELS
VINP SQUARE WAVE PERIOD IN ns
FIGURE 7. ISL55142 ICC 1 AND 2 CHANNELS ACTIVE
FIGURE 8. ISL55143 ICC 1, 2, 3, 4 CHANNELS ACTIVE
100 90 80 70 ICC (mA) ICC (mA) 60 50 40 30 20 10 0 3200 1600 800 400 200 100 VCC = 10V 50 25 VINP SQUARE WAVE PERIOD IN ns VCC = 14V VCC = 18V
250 225 200 175 150 125 100 75 50 25 0 3200 1600 800 400 200 100 VCC = 10V 50 25 VINP SQUARE WAVE PERIOD IN ns VCC = 14V VCC = 18V
FIGURE 9. ISL55142 2-CHANNEL ICC @ 10V, 14V, AND 18V
FIGURE 10. ISL55143 4-CHANNEL ICC @ 10V, 14V, AND 18V
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FN6230.0 July 17, 2006
ISL55141, ISL55142, ISL55143 Typical Performance Curves
15.0 13.5 12.0 DELAY (ns) 10.5 9.0 7.5 6.0 4.5 3.0 1.5 1.0V/DIV 0 0.05 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 VINP INPUT OFFSET 1.5 VOLT REFERENCE 0 -tpd DELAY tPDHL +tpd DELAY tPDLH VCC 15.0 VEE - 3.0 0.5V/DIV 0
Device installed on Intersil ISL55141, ISL55142, ISL55143 Evaluation Boards. (Continued)
10ns/DIV
FIGURE 11. PROPAGATION DELAY @ 14V VCC-VEE
FIGURE 12. MINIMUM PULSE WIDTH RESPONSE
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FN6230.0 July 17, 2006
ISL55141, ISL55142, ISL55143 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.4x4A
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGD-10) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.30 2.30 2.30 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.25 4.00 BSC 3.75 BSC 2.40 4.00 BSC 3.75 BSC 2.40 0.50 BSC 0.40 16 4 4 0.60 12 0.50 0.15 2.55 2.55 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 2 3/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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FN6230.0 July 17, 2006
ISL55141, ISL55142, ISL55143 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
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FN6230.0 July 17, 2006
ISL55141, ISL55142, ISL55143 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L20.5x5
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L N Nd Ne P 0.20 0.35 2.95 2.95 0.23 MIN 0.80 NOMINAL 0.90 0.02 0.65 0.20 REF 0.30 5.00 BSC 4.75 BSC 3.10 5.00 BSC 4.75 BSC 3.10 0.65 BSC 0.60 20 5 5 0.60 12 0.75 3.25 3.25 0.38 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 2 3 3 9 9 Rev. 4 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220VHHC Issue I except for the "b" dimension.
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FN6230.0 July 17, 2006
ISL55141, ISL55142, ISL55143 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.252 0.169 0.246 0.0177 20 0o 8o 0o MAX 0.047 0.006 0.051 0.0118 0.0079 0.260 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 6.40 4.30 6.25 0.45 20 8o MAX 1.20 0.15 1.05 0.30 0.20 6.60 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 1 6/98
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
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FN6230.0 July 17, 2006
ISL55141, ISL55142, ISL55143 Thin Quad Flat No-Lead Plastic Package (TQFN)
2X A D D/2 0.15 C A
L36.6x6
36 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220WJJD-1 ISSUE C) MILLIMETERS SYMBOL
2X
MIN 0.70 -
NOMINAL 0.75 0.20 REF
MAX 0.80 0.05
NOTES -
A
0.15 C B
6 INDEX AREA
N 1 2 3 E/2 E
A1 A3 b D D2 E
0.18
0.25 6.00 BSC
0.30
5, 8 -
3.80
3.95 6.00 BSC
4.05
7, 8 -
TOP VIEW
B
E2 e k
A
3.80
3.95 0.50 BSC
4.05
7, 8 -
0.20 0.45
0.55 36 9 9
0.65
8 2 3 3 Rev. 2 04/06
L
/ / 0.10 C 0.08 C
C
N Nd Ne
SEATING PLANE
SIDE VIEW
A3
A1
NX b D2 D2 2
5 0.10 M C A B 7 8 NX k N
(DATUM B)
(DATUM A) (Ne-1)Xe REF. 8
6 INDEX AREA
E2 3 2 1 NX L N 8 e (Nd-1)Xe REF. BOTTOM VIEW E2/2
7
NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
A1 NX b 5
SECTION "C-C"
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6230.0 July 17, 2006

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